Target devices such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices.
Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are high-level compilation and hardware description language (HDL) compilation. EDA tools that perform high-level compilation allow designers to more quickly realize designs for systems by raising the abstraction level from traditional register transfer level (RTL) based design to a computer language description of the system.
After high-level compilation and HDL compilation, designers are able to review compiled designs for their systems to determine how resources have been allocated. If it is determined that a target device does not have sufficient resources to implement a system, a designer may modify the computer language description of the system and recompile it.